1. Technical Field of the Invention
The present invention relates to voltage detection circuitry, and particularly to detecting intermediate reference voltages utilized by memory devices during memory access operations.
2. Description of the Related Art
Dynamic random access memory (DRAM) devices are known to store a single data value as a charge maintained on a memory cell capacitor. An addressed memory cell is accessed by coupling the memory cell capacitor to a bit line, the voltage of which is then sensed by a sense amplifier. The sense amplifier amplifies the voltage on the bit line so that the bit line may be effectively received by input/output circuitry and provided to an external data output pin of the memory device.
In particular, the sense amplifier senses the voltage appearing on a bit line by sensing the voltage differential appearing across a pair of bit lines. A first bit line of the bit line pair is coupled to the addressed memory cell and maintains a voltage/charge representative of the data value stored in the addressed memory cell. The charge appearing on the memory cell capacitor is shared with the charge appearing on the bit line. A second bit line of the bit line pair is set to a reference voltage level by a reference memory cell having a voltage level between a voltage level corresponding to a logic high value and a voltage level corresponding to a logic low value.
Because the capacitance of a memory cell capacitor is markedly smaller than the capacitance of a bit line, it is important to ensure that the bit lines are initially at the same voltage and that the bit line voltage does not vary from bit line to bit line. Accordingly, DRAM devices typically employ equilibrate circuitry to initially short together the bit lines of the bit line pairs and precharge circuitry to drive the bit lines to a desired voltage level at the beginning of each memory access operation. The precharge circuitry may typically include or otherwise utilize a reference generator that generates an output signal at the desired voltage level.
In order to get the largest capacitance in the smallest possible area, the oxide of a DRAM memory cell capacitor must be extremely thin. Since voltages as small as a few volts can weaken or even destroy these thin oxides, it is important that the voltage across the capacitors"" terminals not exceed a predefined critical value. Since one terminal of the capacitor must vary between logic low and logic high voltage levels, depending on the data being written into the cell at the time, the voltage appearing on the other capacitor terminal must be at some intermediate voltage level and must be held relatively constant. Accordingly, DRAM devices typically employ a reference generator that generates an output signal at this intermediate level.
The differential nature of sense amplifiers requires that reference memory cells be used to provide a voltage against which memory cell voltages can be compared. Because memory cells are written with either low logic levels or high logic levels, an intermediate voltage level is required for these reference memory cells. Accordingly, DRAM devices also employ a reference generator that generates an output signal at this intermediate level.
With supply voltages ever decreasing, the difference between voltages representing logic high and logic low values continues to decrease. The decrease in supply voltage levels makes it more important to ensure that each aforementioned intermediate and/or desired voltage levels is maintained close to its predetermined value. Failure to do so can result either in yield loss, if the DRAM device fails functional tests, or in long-term reliability failure, if the DRAM device fails in the users"" application. As a result, existing DRAM devices have employed test circuitry for determining whether these reference generator circuits operate within acceptable limits, i.e., whether the bit lines, reference cells and plate connections are maintained at voltage levels appropriate for normal operation. The test circuitry typically includes a differential amplifier/comparator circuit for comparing the output of the generator circuitry with a test signal, often provided by a bandgap circuit. This test circuitry, however, is overly complex for the purpose of testing reference generator circuitry for generating intermediate voltage levels and thereby occupies an appreciable amount of space in conventional DRAM devices.
Based upon the foregoing, there is a need for more effectively testing the operation of precharge circuitry within semiconductor memory devices.
Embodiments of the present invention overcome the above-identified shortcoming associated with existing test circuitry and satisfy a significant need for a detection circuit for detecting whether reference generator circuitry within a memory device, such as a DRAM device, no longer generates an intermediate reference voltage within a desired range of voltage levels. Instead of utilizing relatively complex differential amplifier circuitry, an embodiment of the present invention may utilize a pair of Schmitt trigger circuits to determine whether the intermediate voltage generated by the reference generator exceeds a maximum threshold voltage level and falls below a minimum threshold voltage level. The detection circuit may include reset circuitry coupled between the output of the reference generator and the input of each Schmitt trigger circuit, for selectively and temporarily placing the input of the Schmitt trigger circuits at logic high and logic low values, before the detection circuit performs voltage detection.
In the event the output of the reference generator circuitry thereafter falls below the minimum threshold voltage level, an output of a first of the Schmitt trigger circuits changes logic values, which thereupon causes an output of the detection circuit to change state. In the event the output of the reference generator exceeds the maximum threshold voltage level, an output of a second of the Schmitt trigger circuits changes logic values, which thereupon causes the output of the detection circuit to change state. In this way, the output of the reference generator may be monitored in an efficient and relatively simple manner.